Definition

Synthesis is the process of converting RTL (Register Transfer Level) code (i.e.., Verilog format) to optimized Gate level netlist to the targeted technology by meeting area, timing and power constraints.

Types of synthesis

There are 2 types of synthesis techniques which are in use to convert RTL code to gatelevel netlist:
1. Logic synthesis
2. Physical aware synthesis

Logic Synthesis

The below flow chart shows the cadence logic synthesis flow to convert RTL code to netlist (almost all tools follow the same flow with minimal changes)

some popular tools for synthesis are:
Genus – Cadence
Design Compiler – Synopsys
Now a days most of the companies are moving to Fusion Compiler (Synosys) instead of Design Compiler. The main advantage of this tool is we can do both synthesis and PnR in the same tool. In other words it is a combination of both Design Compiler & ICC2

Logic synthesis flow

Importing Input files (RTL code and .lib files)
⇩
Elaborate
⇩
Read SDC file
⇩
Sanity checks (check_design, check_timing)
⇩
Generic mapping
⇩
Technology mapping
⇩
Optimization
⇩
DFT (Design For Testability) implementation (Done by DFT team)
⇩
Incremental optimization
⇩
Generating outputs (Netlist, SDC, Scan DEF, Required reports)

Let us see each step of the flow in a detailed way

Inputs of logic synthesis

At first step we will import all required input files to the Genus compiler i.e

• RTL code
• Timing libraries(.lib files)
• SDC (synopsis design constraints)

Elaborate

In this step the tool will elaborate the RTL code which we have given as input during first step. During the elaboration step mainly 3 tasks are performed:

• Data structure: No. of RTL files are given as input to the tool. So, the tool takes all these files and makes a single netlist from all these Verilog files.
• Infers registers: It infers (to make a well informed guess) the decision trees like if..else… statements to mux and latches or flops.
  1. The synthesis tool infers a flip flop whenever a “posedge” or “negedge” construct is present.
  2. Tool infers “if…else…” as mux.
  3. Similarly, case statements are infers as priority encoders.
• HDL optimization: In this step, tool removes dead codes, unloaded outputs, combinational loops, floating inputs, etc..,

Read SDC

Read SDC is a command used to read all the contents of SDC file.SDC means Synopsis Design Constraints. It contains design timing information, wireload models and DRV’S .These constraints are like timing guidelines for the design, tool always follows these constraints.

what is DRV’S: DRV’S stands for Design Rule Violations.Every design should be DRV free.In simple words if we give some limit for the tool to do a task.The tool must do the task in the given limit only.If it fails to perform a task in given limit then DRV’s occurs. DRVs are 4 types:

Max transition, Max Capacitance, Max Fanout, Max Length.

Note: Max transition and Max Capacitance are considered as hard constraints. These two should not violated in the design and mandatory to fix. And Max Fanout and Max length are considered as Soft constraints that means these can be ignored even violate not mandatory to fix.

Sanity checks

Before the mapping stage, we must perfom sanity checks on RTL code and SDC file to check the quality of input files .The various sanity checks are 
check_design: It reports design information like combinational loops, unintended latches, floating inputs, dead codes, multidriven nets.
check_timing: It checks SDC file (mandatory check). It reports any issues present in the file. Some of the issues are:

• Missing clock definition
• Unconstrained endpoints
• Missing Input/output delays for the ports
• Clock reaching to all the sequential elements
• Multi clock driven registers
• Missing slew or load constraints for the ports

Note: If we found any issues in input files during sanity checks we do not proceed we will sent back those input files to Frontend team with describing the issue.

Generic mapping

During generic mapping, tool converts RTL code to the symbolic gate level representation. Tool maps the cells to the generic library. It is independent of technology.

Example of generic netlist

Following “flipflop_generic_netlist.v” shows the example generic netlist for a flipflop.

module flop (clk, reset, next_clk_enable, clk_enable);
input clk, reset, next_clk_enable;
output clk_enable;
wire clk, reset, next_clk_enable;
wire clk_enable;
CDN_flop clk_enable_reg_reg(.clk (clk), .d (next_clk_enable), .sena (1'b1), .aclr (1'b0), .apre (reset), .srl (1'b0), .srd (1'b0), .q (clk_enable));
endmodule

`ifdef RC_CDN_GENERIC_GATE
`else
module CDN_flop(clk, d, sena, aclr, apre, srl, srd, q);
input clk, d, sena, aclr, apre, srl, srd;
output q;
wire clk, d, sena, aclr, apre, srl, srd;
wire q;
reg qi;
assign #1 q = qi;
always
@(posedgeclk or posedgeapre or posedgeaclr)
if (aclr)
qi<= 0;
else if (apre)
qi<= 1;
else if (srl)
qi<= srd;
else begin
if (sena)
qi<= d;
end
initial
qi<= 1'b0;
endmodule
`endif

In this step, logic optimization also done by the tool. Logic optimization means tool removes all unwanted wires, cells, flipflops with constant logic ‘0’ or logic ‘1’.

Technology mapping

During this step, tool maps generic gate to the targeted technology gates by using targeted library files. Targeted technology gates will have gate area, timing and power, this info present in the .lib file.

Example of targetted technology netlist

Following “tech_mapped_netlist.v” shows the example targeted technology netlist for flipflop

module flop (clk, reset, next_clk_enable, clk_enable);
input clk, reset, next_clk_enable;
output clk_enable;
wire clk, n_3, next_clk_enable;
wire clk_enable;
DFFSHQX1 clk_enable_reg_reg(.SN (n_3), .CK (clk), .D (next_clk_enable), .Q (clk_enable));
endmodule

Optimization

During optimization, tool optimizes the design to meet all design constraints (area, timing and power). Some of optimization techniques are changing VT of cells, changing drive strength of cells, logic restructuring, adding repeaters, cloning and buffering.

DFT (Design For Testability) implementation

• DFT is one of the most important process in the SOC design cycle, which helps us in detecting manufacturing defects in the designs.
• DFT engineer works on inserting extra hardware blocks as part of the design itself, for increasing the testability of chips.
• Testing is required to guarantee fault-free chips.
• DFT team will insert scan chains to the design.Scan chains are nothing but adding extra input and enable pin to the flops,these are used to check wheather the flop is working or not by giving test inputs during testing

Incremental optimization

After scan insertion, one more round of optimization has to do that is called Incremental optimization.We will use same optimization techniques as discussed above

Generating outputs

Outputs of logic synthesis are:

• Optimized gatelevel netlist
• SDC
• Scan DEF: Info for scan connection between the flops in the design
• Reports

Physical aware synthesis

Physical aware synthesis is bit advance compared to logic synthesis. Because physical aware synthesis not only converts RTL code to gatelevel netlist but also places the standard cells in the core area to meet all requirements like area, power and timing.

Physical aware synthesis flow is also same as logic synthesis. But some add-ons are there in input files and generating output files.

Input files

• RTL code
• Physical libraries and technology (.lef)
• MMMC file
• Timing libraries (.lib)
• SDC file
• Captables or qrcTech file
• Floorplan DEF (optional)
• UPF – Unified Power Format (optional – only if the design have multiple power domains)

During mapping, tool place standard cells in the core area. If the floorplan DEF is not given as input ,the tool estimates core area based on gate area and places the cell in the core area.

Compared to wireload model synthesis, this method is more accurate. If we use physical aware synthesis, the timing findings before and after actual placement would be more closely related to one another.

Outputs of the physical aware synthesis

• Gatelevel netlist
• SDC file
• Scan DEF
• Reports
• Placed DEF file
• MMMC file

Practical approach for Synthesis

step 1 : Importing input files (RTL code & .Lib Files) → Here in this command ../ means one folder back from the current directory. LIB is the folder name & slow.lib is the file name which we want to use it as library for our design

set_db / .library { ../LIB/slow.lib ../LIB/pll.lib}
set_db / .lef_library { ../LEF/example_tech.lef ../LEF/example_macro.lef ../LEF/pll.lef}

step 2 : Read hdl & Elaborate → The command read_hdl is used to read hdl code (verilog code) here and.v is our input file

read_hdl " ../test/and.v "
elaborate

step 3 :Read SDC file → The command read_sdc is used to read SDC file here example.sdc is our SDC file

read_sdc ../constraints/example.sdc

step 4 : Sanity Checks

check_design
check_timing

step 5 : Generic Mapping → The command syn_generic is used for generic mapping

syn_generic

step 6 :Technology Mapping → The command syn_map is used for technology mapping

syn_map

Note: without generic mapping also we can do directly technology mapping. But the advantage of doing generic mapping is generic mapped file can be mapped with any technology without doing the whole process again.

For instance we run the synthesis, generated the generic mapped file and mapped to 90nm technology but later due to change in requirements we need to map with 65nm technology.In that case we dont need to do whole synthesis again we just use already generated generic map file to map with 65nm technology

step 7 : Optimization → The  command syn_opt is used for optimization

syn_opt

step 8 : Generating Outputs → In this step we will generate outputs.Here we are gerenating outputs in the same directory if we want to generate outputs in different directory then we have to give the path where we want the file

For example
write_sdc > /home/test/output.sdc
In this example output.sdc will be genertaed in the test folder

write_hdl > output_netlist.vg
write_sdc > output.sdc


step 9 : Generating Reports → Generating reports are also similar to generating outputs here only thing will change is the commmands used to generate reports

report area > area.rpt
report timing > timing.rpt
report power > power.rpt

Example of Synthesis template

Here the commands used in the script are tool related commands, if we need to excute the entire commands by one click we need to write all commands in one file just shown in the below example and add extension like .tcl or .pl. Tool Command Language (tcl) ,Perl (pl) are nothing but scripting languages most widely using in VLSI industry. Python (.py) also used for some advanced applications.

If you have any doubts regarding the Synthesis feel free to comment below