PnR (Place and Route) flow is part of ASIC (Application Specific Integrated Circuit) flow which starts after synthesis. It is termed as backend process in ASIC flow. During PnR flow, actual layout of design can be implemented by using EDA tools like cadence – innovus, Synopsys – ICC2 (These two are most famous for PnR). PnR Flow goal is to implement a layout of design for targeted technology without any timing and DRC (Design Rule Check) errors after routing stage. If in case any violations are there after routing, we go for signoff stage. In this signoff stage, all remaining violations (like timing, DRC, LVS, EM and IR) can be fixed.
Flow Chart
Importing input files
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Sanity checks
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Floorplan
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Pre-placement
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Placement
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Pre-CTS
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CTS (Clock Tree Synthesis)
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Post-CTS
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Routing
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Post-Route
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Signoff
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GDSII File
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