Timing library (.lib) is also known as liberty file. It can be readable through human because of it is implemented in ASCII format. These timing libraries generated by the library vendors or foundries.
A typical timing library will have information of standard cells like timing, area and power.Timing can be implemented by using timing models under different operating conditions (PVT).
There are mainly two types of timing models are present to model the timing libraries:
• NLDM (Non Linear Delay Model).
• CCS (Composite Current Source).
NLDM and CCS are used tocalculate the delay of standard cells.So, cell delays are depends on applyingdifferent input transitions and output load capacitances. These input transition and output load capacitances are includes into liberty file in the form of look-up tables.
CCS is accurate compared to NLDM. NLDM is modeled by using voltage source and CCS is modeled by using current source. NLDM modeled libraries run times are faster compared to CCS modeled libraries. And also NLDM modeled libraries are smaller in file size but CCS modeled libraries are very larger in size.
Note: Delay of cells depends on input transition and output load under different operating conditions based on timing models.
Note: The following templates reflects only mandatory content. Depending on the technology and requirements some extra feature would be added to the timing library.
Timing libraries will have 3 parts:
i. Header
ii. LUT (Look-up Table)
iii. Cell definition
Header
• It contains some information which is common for all the standard cells.
• The information is like library name, units, operating conditions and date of creation.
Template of timing library
library (<library_name>);→ timing library name
delay_model :table_lookup;→ it define the delay model of this library
/* unit attributes */
time_unit :<time_unit>;→ units of time (usually in nano seconds, ns)
voltage_unit :<voltage_unit>;→ units of voltage
current_unit :<current_unit>;→ units of current (usually in milliampere, mA)
pulling_resistance_unit :<resistance_unit>;→ units of resistance (usually in kilo ohm, kohm)
leakage_power_unit :<power_unit>;→ units of power (usually in nano watts, nW)
capacitive_load_unit (<value>, capacitace_unit);→ units of capacitance (usually in pico farad, pf)
/*slew and threshold values in percentage to calculate delay*/
slew_upper_threshold_pct_rise : <value>;→ slew upper threshold value of rise percentage
slew_lower_threshold_pct_rise : <value>;→ slew lower threshold value of rise percentage
slew_upper_threshold_pct_fall : <value>;→ slew upper threshold value of fall percentage
slew_lower_threshold_pct_fall : <value>;→ slew lower threshold value of fall percentage
input_threshold_pct_rise : <value>;→ rise signal input threshold percentage
input_threshold_pct_fall : <value>;→ fall signal input threshold percentage
output_threshold_pct_rise : <value>;→ rise signal output threshold percentage
output_threshold_pct_fall : <value>;→ fall signal output threshold percentage
nom_process : <value>;→ nominal process (usually 1 is the value)
nom_voltage : <value>;→ nominal voltage (ex: 1.32V, 0.5V, 1V, 0.8V, etc..,)
nom_temperature : <value>;→ nominal temperature (ex: 125⁰C, -40⁰C, 0⁰C, etc..,)
/*cells in this library works under these operating conditions*/
operating_conditions( <operating_condition_name> );→ this library cells works under this operating conditons
process : <value>;
voltage : <value>;
temperature : <value>;
power_rail( RAIL_VDD, <value>);
power_rail( RAIL_VSS, 0 );
}
Example of header in library file
LUT (Look-up table)
• LUT means look-up table. It can be find just below of header section.
• It’s the prototype of delay, hold, recovery and removal and power.
• Look-up table values are subjected to change inside pin definitions.
Template of look-up table
lu_table_template(<label_of_table>) {
variable_1 :<variable_name>;
variable_2 :<variable_name>;
index_1 (“<variable_1 data points>”);
index_2 (“<variable_2 data points>”);
}
Example of look-up table
Cell definition
- Cell definition section contains cell information like cell name, cell area, leakage power, rail connection for both VDD and VSS.
- This section includes pin definition also. Pin definition contains information like pin direction (input, output or inout), signal level, pin capacitance, rise capacitance, fall capacitance.
- If the pin is output pin then function of the cell (logic of cell).
- State tables are available for every sequential element.
Template of Cell definition in library
cell (<cell_name>) {→ cell name
area :<cell_area>;→ cell area
cell_leakage_power :<leakage_power_value>;→ leakage power
rail_connection( VDD, RAIL_VDD );→ VDD for cell rail connection
rail_connection( VSS, RAIL_VSS );→ VSS for cell rail connection
ff () or latch () → state table for sequential element
pin(<pin_name>) {→ pin name
direction :<pin_direction>;→ pin direction input, output orinout
input_signal_level : RAIL_VDD;→ pin input signal level only if input pin
output_signal_level : RAIL_VDD;→ pin output signal level only if output pin
capacitance : <value>;→ pin capacitance
rise_capacitance : <value>;→ pin rise capacitance
fall_capacitance : <value>;→ pin fall capacitance
function : “<cell_logic>”;→ cell logic only if the pin is output
timing() {→ timing of output pin only if output pin
related_pin : “<pin_name>”;→ related pin name
timing_sense :<pin_unateness>;→ unateness of pin (positive, negative or non unateness)
cell_rise(delay_template_7x7) {→ timing definition by using look-up tables
index_1 (“<7 values>”);
index_2 (“<7 values>”);
values ( <set of values upto 7×7>)
}
Example of Cell definition
State Table example for flipflop
Note: Every Sequential element had a state table
