In Physical Design there are many types of input files used. Let us see each file in a detailed way.

Types of Input Files

Different types of Input Files are listed below:
1. Register Transfer Level (RTL)
2. Timing Library (.lib)
3. SDC (Synopsis Design Constraints)
4. LEF (Library Exchange Format)
5. MMMC (Multi Mode Multi Corner)
6. Netlist
7. DEF (Design Exchange Format) 
8. RC Coefficient
9. SPEF (Standard Parasitic Exchange Format)
10. UPF (Unified Power Format)
11. GDS & OASIS

• RTL stands for Register Transfer Language.
• Its primary usage is to facilitate data transfer from one register to another.
• Usually, RTL code is developed by using HDL (Hardware Description Language) like VHDL or Verilog.
• In other words, building a digital design harnessing sequential and combinational circuits in HDL, such as Verilog or VHDL, which can describe hardware and logical behavior.
• RTL code is independent of technology node, that means same code can be used without any changes for different technology nodes like 90nm, 45nm, 28nm, etc..,
• RTL code is given as an input to the synthesis tool, then tool implements the design and generates “Netlist” as an output which is also a Verilog format.

Click on RTL for more detailed information Register Transfer Level (RTL)

Timing library (.lib)

Timing library (.lib) is also known as liberty file. It can be readable through human because of it is implemented in ASCII format. These timing libraries generated by the library vendors or foundries.
A typical timing library will have information of standard cells like timing, area and power.Timing can be implemented by using timing models under different operating conditions (PVT).

There are mainly two types of timing models are present to model the timing libraries:
     •  NLDM (Non Linear Delay Model).
     •  CCS (Composite Current Source).

NLDM and CCS are used tocalculate the delay of standard cells.So, cell delays are depends on applyingdifferent input transitions and output load capacitances. These input transition and output load capacitances are includes into liberty file in the form of look-up tables.

CCS is accurate compared to NLDM. NLDM is modeled by using voltage source and CCS is modeled by using current source. NLDM modeled libraries run times are faster compared to CCS modeled libraries. And also NLDM modeled libraries are smaller in file size but CCS modeled libraries are very larger in size.

Note: Delay of cells depends on input transition and output load under different operating conditions based on timing models.

Note: The following templates reflects only mandatory content. Depending on the technology and requirements some extra feature would be added to the timing library.

Timing libraries will have 3 parts:
i.   Header
ii.  LUT (Look-up Table)
iii. Cell definition

Click on .lib for more detailed information about Timing Library (.Lib)

SDC File

• SDC stands for Synopsys Design Constraints. It was developed by Synopsys Company.
• It is an open source file with “.sdc” as an extension.
• SDC commands are developed based on TCL (Tool Command Language) which is supported by almost all EDA tools.
• By using SDC, timing, area and power constraints are provides to the tools like synthesis, PnR and STA.
• It contains design timing information like clock definitions, generated clocks, virtual clocks, clock transitions, input port delays, output port delays, wireload model, timing exceptions and DRVs, etc…
• Some of the important SDC constraints are listed below:
  • create_clock
  • create_generated_clock
  • set_clock_transition
  • set_clock_latency
  • set_clock_uncertainity
  • set_input_delay
  • set_output_delay
  • set_false_path
  • set_multicycle_path
  • set_max_delay
  • set_min_delay
  • set_max_fanout
  • set_max_transition
  • set_max_capacitance

Click on SDC for more detailed information about Synopsys Design Constraints (.SDC)

LEF File

LEF stands for Library Exchange Format. It is also termed as physical library, because this file contains physical abstract information of Layers and standard cells / macros. It is implemented in ASCII format, so it can be readable by human.These physical libraries generated by the library vendors or foundries.
Physical libraries are two types:
Technology LEF
Standard cell/macro LEF

Technology LEF

Technology LEF will have information of library version, units, manufacturing grid and layers information.

Standard Cell/Macro LEF

This LEF contains abstract view of each and every standard cell. The cell LEF contains basic information like Cell name, Class, Origin, Size, Symmetry, Pin information(pin name, direction, shape, etc…)

Click on .Lef for more detailed information about Library Exchange Format (.Lef)

NETLIST

For a digital design, netlist contains the standard cells, logical connectivity among the cells and net names present in the design and all this information will be in textual format. So, netlist is a list of nets that describe how standard cells are connected to one another to create a specific design. Like the way, for an analog design, a netlist contains transistors, capacitors and resistors in the design.

There are 2 types of netlists:

• Flat netlist
• Hierarchical netlist

Click on Netlist for more detailed information about Netlist

DEF File

DEF stands for Design Exchange Format. DEF file basically contains placement information of standard cells, macros, routes, I/O ports or pin location, Blockages, etc…, This file is given as an input of EDA tool. We can generate this file at every stage of PnR flow. Click on DEF for more detailed information about DEF

RC Coefficient

In VLSI, RC Co-efficient file contains information about resistance (R) and capacitance (C) values associated with the interconnects and components in an integrated circuit.

Resistance (R): We know that resistance means the opposition encountered by electric current as it flows through a conductor. In the context of RC coefficient files, resistance values are assigned to various metal interconnects and other conductive paths that link different components, such as transistors and gates on the chip. The resistance values help estimate the power dissipation and voltage drop along the interconnects, which are crucial considerations for ensuring proper signal integrity and minimizing power losses in the chip.Click on RC Coefficient for more detailed information about RC-Coefficient

SPEF

SPEF stands for “Standard Parasitic Exchange Format”.It is commonly used file format to represent the parasitic information of a design. Parasitics means the unwanted resistance, capacitance and inductance are formed in the design interconnects (wires and vias).

The SPEF file provides accurate and detailed information about the parasitics and their impact in the design in an ASCII format (human readable).It can be created using parasitic extraction tool (like QRC or StarRC) and not possible to create manually by the user.The SPEF file supports specifications of all the cases like best, worst and typical.Click on SPEF for more detailed information about SPEF

UPF

UPF stands for “Unified Power Format”. This file is mainly associated with low-power (Multi-power domains) designs and important for optimizing power consumption in modern electronic devices. This file describes the power intent or power management specifications for low-power designs. This UPF file was implemented using TCL Programming.Click on UPF for more detailed information about UPF

GDS and OASIS

To get the accurate physical layout information a special file format is needed. In the early 1970’s a file format called Masterslice used to represent the physical layout of a design which is developed by calma company. But Masterslice had limitations, and designs became more complex and advanced, the need for the a more efficient format arose. This led to the development of the GDS file format.Click on GDS & OASIS for more detailed information about GDS & OASIS