# VLSI TALKS > The Freshers Choice ## Posts - [Unified Power Format (UPF)](https://vlsitalks.com/physical-design/upf/): UPF File UPF stands for “Unified Power Format”. This file is mainly associated with low-power (Multi-power domains) designs and important for optimizing power consumption in modern electronic devices. This file describes the power intent or power management specifications for low-power designs. This UPF file was implemented using TCL Programming. The following flow diagram gives the […] - [DV INTRODUCTION](https://vlsitalks.com/design-verification/dv_introduction/): Why UVM After learning sv and doing small projects in sv we start learning UVM. While learning UVM everyone’s internal question is why this UVM when having sv (it’s obvious question after seeing the macros, extending classes and complexity in UVM) Now I’ll try my level best to tell the importance and significance of UVM […] - [GDS & OASIS](https://vlsitalks.com/physical-design/gds-oasis/): To get the accurate physical layout information a special file format is needed. In the early 1970’s a file format called Masterslice used to represent the physical layout of a design which is developed by calma company. But Masterslice had limitations, and designs became more complex and advanced, the need for the a more efficient […] - [Standard Parasitic Exchange Format (SPEF)](https://vlsitalks.com/physical-design/spef/): SPEF stands for “Standard Parasitic Exchange Format”.It is commonly used file format to represent the parasitic information of a design. Parasitics means the unwanted resistance, capacitance and inductance are formed in the design interconnects (wires and vias). The SPEF file provides accurate and detailed information about the parasitics and their impact in the design in […] - [RC Coefficient](https://vlsitalks.com/physical-design/rc_coefficient/): In VLSI, RC Co-efficient file contains information about resistance (R) and capacitance (C) values associated with the interconnects and components in an integrated circuit. Resistance (R): We know that resistance means the opposition encountered by electric current as it flows through a conductor. In the context of RC coefficient files, resistance values are assigned to […] - [BASICS -1](https://vlsitalks.com/physical-design/basics-part-1/): Hi guys welcome to basics part 2 today we are going to see about MOSFET. Before going to know about MOSFET you must know about transistor. What is a Transistor? A transistor is a semiconductor device which has 3 terminals. It is used for switching as well as amplification.It is a current controlled device The […] - [Multi Mode Multi Corner](https://vlsitalks.com/physical-design/mmmc/): MMMC means Multi Mode Multi corner. This file is used to analyze the design in different Modes and corners.Because the chip after manufacture have to work properly for different temperatures, voltage, and while manufacturing there might be some process variations which leads to variation in delays (expected delays will not come).This MMMC file usually develop […] - [Design Exchange Format (DEF)](https://vlsitalks.com/physical-design/def/): DEF stands for Design Exchange Format. DEF file is a standardized data file that represents the physical layout of design. This file is given as an input to the EDA tool. We can generate this file at every stage of design flow. To send placement information from one stage to another stage. By using this […] - [SIGN-OFF](https://vlsitalks.com/physical-design/signoff/): Introduction Signoff is the process of verifying the design at final stage before going to the tape out. Clean signoff reports are the green signal to the fabrication because clean signoff reports ensure the design satisfies all the required specifications and constraints at the final stage. Signoff tools are the analysis tools only, but PnR […] - [ROUTING](https://vlsitalks.com/physical-design/routing/): What is routing Routing is the process of creating physical connections between or among the signal pins by following DRC rules and also after routing timing (setup and hold) have to meet. Types of routing Usually there are three types of routings available which are mentioned below: Pre-routing – also known as power routing which […] - [CTS (CLOCK TREE SYNTHESIS)](https://vlsitalks.com/physical-design/cts/): What is CTS CTS (Clock Tree Synthesis) is the process of connecting the clock from clock port to the clock pin of sequential cells in the design by maintaining minimum insertion delay and balancing the skew between the cells using clock inverters and clock buffers. Dont worry about the terms insertion delay,skew. You will get […] - [PLACEMENT](https://vlsitalks.com/physical-design/placement/): Placement is the process of placing of all standard cells that are present in netlist by the tool into the core area.Tool also optimizes the design while placing. During placement trail routing also can be done by the tool. Placement can be done by the tool in 3 different techniques, which are Timing driven placement […] - [POWER PLAN](https://vlsitalks.com/physical-design/powerplan/): Before going to know about Power Planning in ASIC designs. Let us raise a question, why do we need power planning? In fact, in higher node technologies power planning is not a big task, area, and performance were the things are more concerned while designing. But while technology got advanced (lower technology nodes), the power […] - [FLOORPLAN](https://vlsitalks.com/physical-design/floorplan/): What is Floorplan? Floorplan is simply the planning of where things will be placed in an orderly manner.In simple words its similar to house construction,when you are planning to construct a house first we need a plan right! similary In PD also we need floorplan. Floorplan is the major stage in the PnR flow. It […] - [PnR FLOW](https://vlsitalks.com/physical-design/pnr-flow/): PnR (Place and Route) flow is part of ASIC (Application Specific Integrated Circuit) flow which starts after synthesis. It is termed as backend process in ASIC flow. During PnR flow, actual layout of design can be implemented by using EDA tools like cadence – innovus, Synopsys – ICC2 (These two are most famous for PnR). […] - [Register Transfer Level (RTL)](https://vlsitalks.com/physical-design/rtl-file/): RTL stands for Register Transfer Level. Its primary usage is to facilitate data transfer from one register to another. Usually, RTL code is developed by using HDL (Hardware Description Language) like VHDL or Verilog. In other words, building a digital design harnessing sequential and combinational circuits in HDL, such as Verilog or VHDL, which can […] - [Timing Library (.lib)](https://vlsitalks.com/physical-design/lib/): Timing library (.lib) is also known as liberty file. It can be readable through human because of it is implemented in ASCII format. These timing libraries generated by the library vendors or foundries. A typical timing library will have information of standard cells like timing, area and power.Timing can be implemented by using timing models […] - [Netlist](https://vlsitalks.com/physical-design/netlist/): Exploring the Heart of VLSI Design: Introducing Netlist! What is Netlist Netlist, a crucial representation in VLSI design, outlines the connectivity of an electronic circuit in textual format. It defines the interconnections between components like transistors, gates, and flip-flops, enabling complex tasks within a chip.So, netlist is a list of nets that describe how standard […] - [Library Exchange Format (LEF)](https://vlsitalks.com/physical-design/lef/): LEF stands for Library Exchange Format. It is also termed as physical library, because this file contains physical abstract information of Layers and standard cells / macros. It is implemented in ASCII format, so it can be readable by human.These physical libraries generated by the library vendors or foundries. Physical libraries are two types: Technology […] - [SDC](https://vlsitalks.com/physical-design/sdc/): SDC stands for Synopsys Design Constraints. It was developed by Synopsys Company. It is an open source file with “.sdc” as an extension. SDC commands are developed based on TCL (Tool Command Language) which is supported by almost all EDA tools. By using SDC, timing, area and power constraints are provides to the tools like […] - [SYNTHESIS](https://vlsitalks.com/physical-design/synthesis/): Definition Synthesis is the process of converting RTL (Register Transfer Level) code (i.e.., Verilog format) to optimized Gate level netlist to the targeted technology by meeting area, timing and power constraints. Types of synthesis There are 2 types of synthesis techniques which are in use to convert RTL code to gatelevel netlist:1. Logic synthesis2. Physical […] - [INPUT FILES](https://vlsitalks.com/physical-design/inputfiles/): In Physical Design there are many types of input files used. Let us see each file in a detailed way. Types of Input Files Different types of Input Files are listed below:1. Register Transfer Level (RTL)2. Timing Library (.lib)3. SDC (Synopsis Design Constraints)4. LEF (Library Exchange Format)5. MMMC (Multi Mode Multi Corner)6. Netlist7. DEF (Design […] - [BASICS](https://vlsitalks.com/physical-design/basics/): In this post we are going to see some basics First thing you need to know is Physical Design is not a rocket science. Anyone can learn easily with little effort. Remove the fear in your mind and start learn with excitement Lets get into the topic There are 2 main components we need to […] ## Pages - [EMIR](https://vlsitalks.com/emir/) - [DESIGN VERIFICATION](https://vlsitalks.com/physical-verification-2/) - [About US Mobile](https://vlsitalks.com/about-us-mobile/) - [about- mobile](https://vlsitalks.com/home-mobile-2/) - [STA](https://vlsitalks.com/sta/) - [PV](https://vlsitalks.com/pv/) - [Home - mobile](https://vlsitalks.com/about-us-mobile/home-mobile/) - [Privacy Policy](https://vlsitalks.com/privacy-policy/) - [About Us](https://vlsitalks.com/about-us/) - [Home - VLSI TALKS](https://vlsitalks.com/) [comment]: # (Generated by Hostinger Tools Plugin)