Why UVM
After learning sv and doing small projects in sv we start learning UVM.
While learning UVM everyone’s internal question is why this UVM when having sv (it’s obvious question after seeing the macros, extending classes and complexity in UVM)
Now I’ll try my level best to tell the importance and significance of UVM in industry.
UVM is a methodology used for verifying DUT.
If we are using UVM for verification of DUT then why to learn SV?
UVM is not a language it is a methodology which is derived from SV(System Verilog).
In SV we need to build every thing right from scratch it makes the verification time consuming process and complex.
To make the verification environment easy and efficient we use UVM.
UVM is just like instant everything is already declared we just need to use them this makes the UVM popular.
EX:-for suppose if we want to make tomato pickle,We don’t do tomato harvest for months right instead of what we do we just bring tomatoes from market and necessary things and make the pickle instantly. The tomotoes are harvested by some one before right.
Just like this, UVM is simple and instant one because the implementation is already declared there in SV we just need to use them
When everything(methods) are already declared there it makes ours work easy we just need to use them where we need. This make our verification efficient in less time
After learning UVM is there any need of SV?
see I already said that UVM is a methodology which is derived from SV. To use the methods or tools provided by UVM we must have a good knowledge in SV.
(If there are no tomotoes can we make a tomoto pickle?)
Just like the example SV is the base or root for UVM.
