Register Transfer Level (RTL)

• RTL stands for Register Transfer Level.
• Its primary usage is to facilitate data transfer from one register to another.
• Usually, RTL code is developed by using HDL (Hardware Description Language) like VHDL or Verilog.
• In other words, building a digital design harnessing sequential and combinational circuits in HDL, such as Verilog or VHDL, which can describe hardware and logical behavior.
• RTL code is independent of technology node, that means same code can be used without any changes for different technology nodes like 90nm, 45nm, 28nm, etc..,
• RTL code is given as an input to the synthesis tool, then tool implements the design and generates “Netlist” as an output which is also a Verilog format.

Example of RTL code for D flipflop in verilog language

moduledff(clock,
reset,
d_in,
Q_out,
Qb_out);
always@(posedge clock)
begin
if(reset)
Q_out<= 1'b0;
else
Q_out<= d_in;
end
endmodule